Digital Circuit Design Revision

Block 1

Analog vs Digital

Analog: have values across a continuous range
- ambiguity
Digital: only takes discrete values 0 and 1
- only one interpretation
- Flexibility
- programmability
- speed
- economy
- reproducing results
IC(Integrated Circuits)
Position Number System: Decimal, Binary, Octal, Hexadecimal
MSD(MSB) & LSD(LSB)
Conversion
- to decimal: power
- decimal to other bases: divide(Integer) & multiply(Fractional)
- among any base that is any power of 2: group bits
Arithmetic
- carry & borrow
Negative numbers
- Sign-Magnitude Representation: sign bit
- Two’s Complement: invert +1
- Overflow
Floating Point

store both large and small numbers
- IBM System 360/370: ${(-1)^s0.f*16^{e-64}}$ s|7-bits e|24-bits f
- DEC PDP 11/VAX: ${(-1)^s0.1f*2^{e-128}}$ s|8-bits e| 23-bits f
- IEEE-754: ${(-1)^s1.f*2^{e-127}}$ s|8-bits e| 23-bits f
- excess-3 exponent code: ${(-1)^s1.f*2^{e-3}}$ s|3-bits e|4-bits f
Code
- binary codes: use binary to represent data
- BCD: use 4-bit binary to represent decimal
  - precise decimal math
  - more memory
- Gray Code
- ASCII
- Unicode
Parity Checking
- a simple error detection, only 1 bit
- Even-parity code: set the parity bit to 0 if there’s an even number of 1s
- Odd-parity code: set the parity bit to 0 if there’s an odd number of 1s

some very important theorems:
- (X + Y)(X + Z) = X + YZ – when you meet a PoS problem, this is very useful
- X(X + Y)=X <-- X + XY = X
- XY + X’Z + YZ = XY + X’Z , (X + Y)(X’ + Z)(Y + Z) = (X + Y )(X’ + Z) Consensus “add a 1(X+X’) term to prove”
- X + X’Y = X + Y <-- X(X’ + Y) = XY
- Duality
- De Morgan’s
- Shannon’s
find complement: duality + inverse
minterm & maxterm
- minterms always equal 1
- maxtrems always equal 0
- eg. XYZ, X+Y+Z, X’Y’Z, X’+Y’+Z --> m7, M0, m1, M6
- ${M_0=\overline{m_0}}$
SoP & PoS
- F = X’Y’Z’ + X’Y’Z + X’YZ’ + XY’Z’ + XY’Z – ${F=\Sigma m(0,1,2,4,5)=\Pi M(3,6,7)}$
- SoP -> PoS : find F’, complement again , simplify with De Morgan’s law
- find standard SoP: multiply(X+X’) – use distributive theorem
- find standard PoS: add(XX’) – use distributive theorem

	${T_p}$ (ns)	$P$ (mW)	Noise Margin(mV)	Fan-out
TTL	9	10	400	10
CMOS	18	0.01	1050(OH),1340(OL)	<=50

Fanin: the number of inputs a gate can have
Fanout: maximun number of inputs an output can drive
Impedance
Propagation delay: the amount time needed for a input change produce an output change
Noise Margin: maximum external noise can be added to inputs that will not cause an undesired change

why K-Maps:
- simplify the combinational circuit --> find grouping of 1’s
Prime Implicants
- the size of each group is maximised
- this makes a MSP(minimal SoP)
EPIs
- group containing a minterm that is not covered by other overlapping groups
don’t care case

d(X,Y,Z), can be grouped in 1’s groups

Glitch: A momentary unexcepted output change (short pulse) when an input changes; usually caused by gate propagation delays
Hazards

A timing hazard exists in a combinational circuit when it produces an output glitch when one or more inputs change.
- A static-1 hazard is a pair of input combinations that: (i) differ in only one input variable and (ii) both give a 1 output; such that it is possible for a momentary 0 output( 0 glitch ) to occur during a transition in the differing input variable – for SoP case
  
  Note: One variable changing will cause problem because there is a NOT Gate propagation delay which makes 2 AND Gates cannot change at the same time. Adding a redundant group holds the final output at the correct signal level. One variable changing happens when two 1s are neighbors in K-Map but are in 2 separate groups.
- A static-0 hazard is a pair of input combinations that: (i) differ in only one input variable and (ii) both give a 0 output; such that it is possible for a momentary 1 output to occur during a transition in the differing input variable. – for PoS case
- how to avoid it?
  
  add a redundant group

how many states or need how many FFs?

$state=2^n$
Synchronous clocked sequential circuit/ synchronous clocked state machine?

combinational circuit, state register, clock pulses
metastability?

happens when both inputs are halfway between 0 and 1

not a valid state

stay in metastability forever if there is no noise

->how to cause?

caused by “asynchronous inputs” that do not meet flip-flop setup and hold times.
oscillation & undefined

SR->1 simultaneously–0,0 undefined

SR->0–oscillation
implement with NAND gates
why Control line/ enable?

control when SR can be changed/ written with new value
why D Latch?

eliminate the indeterminate state

set and reset are always complement of each other
Why Flip-Flop?

eliminate Race conditions
Why master-slave?

Isolate output from input, output cannot change continuously with input

Input must have a stable setup time
Why JK Flip-Flop?

avoid indeterminate state

catching behavior?

JK are not held valid during the entire period when CLK is active for master

1’s catching: output changes to 1 even though K is 1 J is 0 at the end of triggering pulse

0’s catching: output changes to 0 even though K is 0 J is 1 at the end of triggering pulse
why edge-triggered?

only set outputs on clock pulse transitions

solve catching behavior.

Moore & Mealy machine?

Moore: output=F(current state)

Mealy: output=F(current state, input)
State machine?

Next-state logic

State memory/ State register

Output logic

Control	Function
0	Add
1	Subtract